DSP Builder technology allows you to go from system definition/simulation using the industry-standard The MathWorks/Simulink tools to system implementation in a matter of minutes.
The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore® blocks and generates VHDL files and tool command language (Tcl) scripts for synthesis, hardware implementation, and simulation.
Altera and The Mathworks work in close collaboration to ensure that you get the price/performance benefits of Altera® FPGAs while leveraging Simulink, the industry-leading tool for model-based design from The MathWorks.
Altera's Simulink-to-FPGA synthesis technology is unique in the industry in that it now supports timing-driven synthesis of a Simulink design representation.
This technology allows you for the first time to automatically generate timing-optimized register transfer level (RTL) code based on high-level Simulink design descriptions. With this new DSP Builder feature, you can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes. This is a significant productivity savings compared to the hours, if not days, required to hand-optimize HDL code. For more information, view advanced blockset DSP Builder libraries.
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